In recent years, in a semiconductor device constituted by semiconductor integrated circuits, high integration has undergone great development. In particular, in semiconductor devices of MIS (metal insulated semiconductor) type, miniaturization and high performance of elements such as transistors have been promoted in order to cope with high integration, and there is a demand for further miniaturization and high performance.
In a process for forming conductors of such a semiconductor device, plasma processing including plasma CVD or plasma etching has been increasingly utilized. This is because in the process for forming conductors of a semiconductor device, there is a limitation regarding the amount to be subjected to heat treatment because of diffusion of impurities, the heat resistance of a metal material for conductors and the like, and the amount to be subjected to heat treatment can be reduced by the plasma process.
Furthermore, in recent years, copper (Cu) conductor may be introduced for further high performance, and a damascene method is used to form copper (Cu) conductors. In this case, the plasma process is utilized increasingly.
Thus, the plasma process is used, not only for etching but also for forming a film, and utilization of the plasma process tends to be increased year by year. However, with the increased utilization of the plasma process, device damage due to the plasma process tends to occur. This is generally called “plasma charging damage”, and has gained attention recently.
In a semiconductor device that is subjected to such plasma charging damage, the device characteristics are deteriorated, so that the semiconductor device is defective. In the problem of plasma charging damage, in particular, deterioration in the reliability of gate insulating films constitutes a serious problem.
Hereinafter, plasma charging damage will be described with reference to FIGS. 11 and 12. FIG. 11 shows partial cross-sectional views of a configuration of a conventional semiconductor device. FIG. 11A is a cross-sectional view taken along the normal direction of a semiconductor substrate constituting a semiconductor device, and FIG. 11B is a cross-sectional view taken along a line C-C′ shown in FIG. 11A.
As shown in FIG. 11A, the conventional device includes an n-type silicon substrate 21. In the silicon substrate 21, a plurality of element separations 22 are formed so as to be exposed on the silicon substrate 21 at a predetermined interval by a STI (Shallow Trench Isolation) method.
Between the element separations 22 on the silicon substrate 21, an n-channel MOS transistor is formed with a p-well 23 formed in the internal portion of the silicon substrate 21, a gate insulating film (film thickness: 2.2 nm) 26, a gate electrode 27 formed of n+ polysilicon, and a source (n+) region 24a and drain (n+) region 24b provided in a surface layer portion of the silicon substrate 21.
The gate insulating film 26 and the gate electrode 27 are formed so as to be aligned with each other, and in the opposite side faces thereof, a side wall (side face protective film) 28 is formed so as to cover the opposite side faces. Reference numeral 25 is an n+ region and is an active region that serves as a source region or a drain region of another transistor.
Furthermore, an underlying interlayer insulating film 30 and an interlayer insulating film 32 are laminated sequentially on the silicon substrate 21 to realize multilayer wiring. Conductors 31a to 31c are formed in the underlying interlayer insulating film 30. The conductors 31a to 31c are copper conductors (thickness: 500 nm) formed by the damascene method and embedded in the underlying interlayer insulating film 30.
The conductor 31a is a conductor for gate electrode connection that is connected to the gate electrode 27 via a W (tungsten) plug 29b. The conductor 31c is a conductor for source and drain connection that is connected to the n+ region 25 via a W (tungsten) plug 29a. The conductors 31a and 31c are formed in a strip shape, as shown in FIG. 11B.
The W plugs 29a and 29b are formed by filling contact holes formed in the underlying interlayer insulating film 30 with tungsten. The W plug 29a is formed so as to be connected to the n+ region 25, and the W plug 29b is formed so as to be connected to the gate electrode 27.
The conductor 31b is a dummy conductor for ensuring smoothness in the CMP (chemical mechanical polishing) process performed in the damascene method, and is formed adjacent to the conductor 31a. As shown in FIG. 11B, for the conductor 31b, a plurality of conductors are provided and each is formed in a square shape. The conductor 31b is insulated by the underlying interlayer insulating film 30 and the interlayer insulating film 32 at its entire circumference and thus is electrically suspended.
FIG. 12 is a cross-sectional view showing a process for forming the interlayer insulating film in the conventional semiconductor device shown in FIG. 11, showing schematically the occurrence of plasma charging damage.
First, the gate insulating film 26 is formed on the silicon substrate 21 provided with the element separation 22 and the p-well 23. Then, the gate electrode 27 is formed on the gate insulating film 26, and the side wall 28 is formed on the opposite side faces of the gate insulating film 26 and the gate electrode 27. Then, the n+ region 25, the source (n+) region 24a and the drain (n+) region 24b are formed by ion implantation to form the underlying interlayer insulating film 30.
Then, the W plugs 29a and 29b are formed in the underlying insulating film 30, and then the conductors 31a to 31c are formed simultaneously. More specifically, trenches are formed in the positions in which the conductors 31a to 31c are to be provided in the underlying interlayer insulating film 30, and copper layers are formed so as to fill the trenches. Thereafter, excess thickness is removed by polishing according to the CMP method.
Then, as shown in FIG. 12, a plasma 33 is generated by a plasma CVD apparatus (not shown) so that the interlayer insulating film 32 is formed. In this case, the conductor 31b is electrically suspended, as described above, and the conductor 31c is connected directly to the silicon substrate 21, so that the charging current from the plasma 33 flows into the gate electrode 27 and the gate insulating film 26. Therefore, the gate insulating film 26 is damaged and thus the device characteristics are damaged.
In order to solve such a problem, JP10-173157A discloses a semiconductor device in which a protection diode connected to the gate electrode is provided on a semiconductor substrate. In the semiconductor device disclosed in JP10-173157A, the charging current that causes plasma charging damage flows off to the ground potential via the protection diode. Therefore, the charging current is suppressed from being applied to the gate insulating film, so that the gate insulating film can be prevented from being damaged.
However, higher integration of the semiconductor device has been making the gate insulating film thinner year by year, and consequently the breakdown voltage of the gate insulating film has become smaller than the junction breakdown voltage of the protection diode. Therefore, as the gate insulating film becomes thinner, the charging current leaking to the gate electrode without flowing into the protection diode is increasing.
The effect of suppressing the plasma charging damage by the protection diode becomes smaller as the gate insulating film becomes thinner, and although the protection diode is provided, the device characteristics are deteriorated by the plasma charging damage.
Furthermore, when the semiconductor substrate on which the protection diode is formed is subjected to the plasma process, a problem as described below may be caused. This problem will be described while describing a method for manufacturing a conventional semiconductor device with reference to FIG. 13.
FIG. 13 is a cross-sectional view showing a process for forming an interlayer insulating film in a conventional semiconductor devise. FIG. 13A is a cross-sectional view taken along the normal direction of a semiconductor substrate, and FIG. 13B is a cross-sectional view taken along a line F-F′ shown in FIG. 13A. The semiconductor device shown in FIG. 13 has a multilayered conductor structure.
First, a gate insulating film 136 is formed on a p-type silicon substrate 131 provided with a plurality of element separations 132 and an n-well 133. As a method for forming the element separation 132, the STI (shallow trench isolation) method can be used. Then, a gate electrode 137 is formed on the gate insulating film (film thickness: 2.2 nm) 136, and a side wall 138 is formed on the opposite side faces of the gate insulating film 136 and the gate electrode 137. The gate electrode 137 is formed of p+ polysilicon.
Then, an active region (p+) 135 that is to serve as the protection diode, a source (p+) region 134a and a drain (p+) region 134b are formed by ion implantation. Thus, a p-channel MOS transistor provided with the gate insulating film 136 and the gate electrode 137 is completed. Thereafter, a plasma is generated with a plasma CVD apparatus (not shown) to form a first interlayer insulating film 140.
Furthermore, a contact hole is formed in the first interlayer insulating film 140 and filled with tungsten, so that W plugs 139a to 139c are formed. Thereafter, conductors 142a, 142b, 143 and 144 are formed simultaneously by the damascene method. These conductors are copper conductors (thickness: 500 nm) and embedded in the first interlayer insulating film 140.
The conductor 142a is formed so as to be connected to the gate electrode 137 via the W plug 139c and be connected to the active region 135 via the W plug 139b. The conductor 142b is formed so as to be connected to the active region 135 via the W plug 139a. 
On the other hand, as seen from FIG. 13B, the conductors 143 and 144 are dummy conductors for ensuring smoothness in the CMP (chemical mechanical polishing) process that is performed in the damascene method. The conductors 143 and 144 are insulated by a first insulating layer 140 and a second insulating layer 141 and are electrically suspended.
Then, a plasma is generated with a plasma CVD apparatus (not shown) to form a second interlayer insulating film 141 on the first interlayer insulating film 140. Thereafter, in the same manner as in the process as described above, W plugs 148a and 148b are formed in the second interlayer insulating film 141, and further, conductors 145a, 145b and 146 are formed. The conductor 146 is a dummy conductor as the conductors 143 and 144 and positioned immediately above the conductors 143 and 144.
Thereafter as shown in FIG. 13, a plasma is generated with a plasma CVD apparatus (not shown) to form a third interlayer insulating film 147 on the second interlayer insulating film 141. Thus, a semiconductor device having a desired multilayered conductor structure can be obtained by repeating formation of interlayer insulating films, formation of W plugs, and formation of conductors.
As described above, the first interlayer insulating film 140, the second interlayer insulating film 141 and the third interlayer insulating film 147 are formed by a plasma process with a plasma CVD apparatus (not shown), and rays in the ultraviolet region are radiated from the plasma toward the silicon substrate 131 during the plasma process. When such rays in the ultraviolet region are incident on the active region 135, a phenomenon occurs in which the rectification property of the diode is lost, depending on the amount of the incident rays, and leakage current in the forward direction between the active region 135 and the n-well 133 increases.
When such a phenomenon occurs, even if an electric field is applied in the reverse direction (the direction from the silicon substrate to plasma), the charging current from the plasma flows off to the ground potential via the protection diode, which reduces an electrical stress to be applied to the gate insulating film 37.
However, in the example of FIG. 13, the conductor 144 is positioned immediately above the active region 135 during formation of the second interlayer insulating film 141, and one conductor 146 is positioned immediately above the active region 135 during formation of the third interlayer insulating film 147. In FIG. 13B, reference numeral 145 denotes a region obtained by projecting the active region 135 on the cross-sectional plane of the first interlayer insulating film 140 along the normal direction of the silicon substrate 131.
For this reason, a part of the rays in the ultraviolet region radiated from the plasma to the protection diode is absorbed by the conductor 144 during the formation of the second interlayer insulating film 141 and absorbed by the conductor 144 and the conductor 146 during the formation of the third interlayer insulating film 148. In this case, the amount of the light incident to the active region 135 is not sufficient, and furthermore it can be said that the generated leak current in the forward direction is small.
Therefore, when an electric field is applied in the reverse direction, a part of the charging current from the plasma does not flow through the protection diode, and is directed to the gate insulating film 136, which applies electrical stress to the gate insulating film 136, and thus the device characteristics are damaged. Furthermore, in the plasma process, the voltage waveform in a plasma CVD apparatus may be switched, and it can be said that not infrequently, the electric field may be applied to the silicon substrate 131, not in the forward direction, but in the reverse direction
Thus, in the example of FIG. 13, although the protection diode is formed, when an electric field is applied in the reverse direction both during the formation of the second interlayer insulating film 141 and during the formation of the third interlayer insulating film 147, electrical stress is applied to the gate insulating film 136 twice. Therefore, it is pointed out that there is a limitation regarding the role of the protection diode.